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Samsung breaks through a 20nm technology barrier at its newly opened 300mm wafer facility

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Samsung Electronics' Hwasung L16 300mm wafer facility

Seoul (iTers News) - Samsung Electronics Co., Ltd. broke through a 20nm(nanometer; one billionth of a meter) design rule barrier at its newly opened 300 mm wafer facility, cutting a groundbreaking path to stay immune from cyclical freefalls in prices of DRAM chips

The world’s memory chip market leader said today it has started a mass production of 20nm-class geometry-wide 2Gb DDR3 SDRAM chip in what the company said is the world’s first ever.

The 20nm-class 2Gb DDR3 SDRAM chips are now rolling off its newly established 300mm wafer facility at Samsung Nano City Complex in Hwaseong City, Gyeonggi Province, the company said.

Called after the width of a circuitry that form circuits of a chip, the 20nm–class design rule is a measure of the chip’s transistors, or circuits sitting somewhere between 20 nanometer and 30 nanometers apart from each other on a silicon die.

Big gains in productivity  

The narrower the in-between distance among transistors of a chip is, the shorter distance electrons travel back and forth. As a result, the chip can write and read data far faster, and consume less power. More importantly, the technological breakthrough translates into big gains in productivity.

Compared with a predecessor 30nm-class design technology, the 20nm manufacturing process consume 40% less power, but allows the chip maker to produce 50% more chips per wafer.

The hefty gains in productivity enable Samsung to produce 2Gb DDR3 DRAM chips at a unit cost of below US$1, paving the way for the company to make money even at current price level that plunges somewhere between US$1 and US$ 60 cents.

The improvements in productivity also allow the chip maker to undercut competitors on costs.

To attain the 20nm design rule technology, Samsung has installed an array of cutting-edge wafer fabrication equipment – a set of immersion photolithography equipment and double-patterning tools at the newly-opened 300 wafer fabrication facility.

Weather out price freefalls 

At a opening ceremony of the new 300mm wafer facility, Kun-Hee Lee, chairman with Samsung Electronics, said, “The global semiconductor industry is in a period of fierce cyclical volatility, so the opening of this new memory fabrication facility and the mass-production of the world ‘s first 20nm-class geometry DRAM chips are an important watershed achievement for Samsung to consolidate a leadership in global memory chip market.”

Samsung has invested a total of 12 trillion won to build the new 300mm wafer facility.

Called as a Line-16, the facility is the world’s largest and advanced wafer fabrication line ever, according to Samsung, occupying a workspace of 198,000 square meters.

The facility is housed in a 12 story-high building that accommodates other supporting utilities like electricity power back-up and water treatment facilities, too.

Yet, the new 3000mm wafer fabrication clean room isn’t designed to house EUV, or extreme ultra violet photolithography equipment, according to Samsung.

The EUV photolithography technology has been around for years, rapidly emerging as a next generation of lighting source technology, but is still too expensive to be commercially available.

EUV technology still out of reach 

Instead, Samsung Electronics has used an existing ArF light source-based immersion technology to trace lines of ultra-tiny 40nm pitches on a silicon die, and then inserted one more line in-between to pattern 20nm pitches using what’s called a double -patterning technology.

Samsung started construction of the Line-16 facility in May 2010 and ended up ed installing equipment for clean rooms this May. Test production began in June, and the facility was ready for mass production in August.

Starting this month, Samsung also began mass production of high-performance 20nm-class NAND flash memory chips, with a projected volume of more than 10,000 12-inch wafers monthly.

Samsung also plans to ramp up production of NAND flash memory to meet market demand, and will begin production of more advanced memory semiconductors with high density and performance using 10nm-class* process technology next year.

On top of that, Samsung plans to develop a new 20nm-class DDR3 component in 4Gb density by the end of 2011. It will allow the chip maker to offer a broadest product line-up ever of 4 gigabyte (GB), 8GB, 16GB and 32GB DDR3 modules next year

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